HDL-FPGA Coding Style Guide

Based on all my years of professional and educational experience I'd like to introduce a document detailing general guidelines for VHDL coding style as well as some related to FPGA architecture. 

Even though I've tried to summarize the most important points, it results in a lengthy document, but it still is useful when starting a new project, or as a reference for coding in HDL (VHDL or Verilog) / FPGA.

Link to the document is as follows. ..... ;) ......

Suggestions are welcome in case any of you have a 'guide/point' that I've missed in the doc.

Have a GrAt DaY !