HDL-FPGA Coding Style Guide

Based on all my years of professional and educational experience I'd like to introduce a document detailing general guidelines for VHDL coding style as well as some related to FPGA architecture. 

Even though I've tried to summarize the most important points, it results in a lengthy document, but it still is useful when starting a new project, or as a reference for coding in HDL (VHDL or Verilog) / FPGA.

Link to the document is as follows. ..... ;) ......

Suggestions are welcome in case any of you have a 'guide/point' that I've missed in the doc.

Have a GrAt DaY ! 

Intel - Altera .... concern? happiness??

Much has been said about this great commercial operation: Intel acquires Altera. 

For those who work with FPGAs and even more, for those who likes Altera FPGAs, this news rise a big concern. And if we add that while I was at Intel I saw Intel acquiring and selling whole groups of IC designers as fries potates... my concern escalated to unknown levels. 

I found an interesting article about this topic. It explains very clear, as always when is written by Kevin Morris, concerns and assumptions about the future of this union. 

I leave here the link to the article: 

Altera’s Long Game 

Hope you enjoy it !

Error: "cannot match operand(s) in the condition to the corresponding edges. . ." "An edge descriptor must be applied to an expression of size 1"

Introduction

Recently a student of mine asked me to review her Verilog code because she had problems and could not find how the error was originated. Obviously, the synthesis tool used generated an error message, and obviously that message did not give any idea of ​​what was the source of the problem. The first thing I did, and that sometimes works for me, is to synthesize the code into the tool of competition (X or A), and .... the result was the same: encrypted error message. The second thing that I usually do in these cases is "google" the error message. I did that and I found nothing ! ... I had no other choice but to study the issue and try to find out the source of the error.
Below you can find details of the problem, error messages and finally the solution ....

Encrypted messages Error

ISE generates the following error message:


"ERROR:Xst:904 - "../../RTL_Src/semaforo.v" line 64: An edge descriptor must be applied to an expression of size 1."
 
The Quartus' error message:

"Error (10200): Verilog HDL Conditional Statement error at semaforo.v(64): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct"

The lines of code corresponding to the line number indicated by the error message are:

At first sight, there is nothing wrong with the code. I checked each statement of these lines, every symbol, every name many times and everything looked perfectly fine.
Another thing I did it was to go to the reference error message generated by the tool. When using ISE the error is Xst ISE: 904:

when you double-click on the link of the error, the following message shows up in ISE:

Does it helps the 'help' ?.... nooooo !!!

Quartus directly had no link or further explanation of the error message itself.

Well, after many workarounds; as always, the solution was very simple. Actually the problem was not in the code itself, but in the definition of clk and rst.

These are the first lines of code where E / S are defined:

Can you find the problem ? .....

PROHIBITED continuing reading before finding the error .... :)

Just for saving a few lines of code, clk and rst were defined in the same line as the two bits vectors sensor and button .... so clk and rst are actually defined as vectors of two bits, so the instruction negedge or posedge can not determine which edge to execute.

As usual,  once one found the error, one says: "How come I can’t find it sooner!", "How easy is the solution !", etc. etc ... What I did find strange is that compilers can not generate a simpler error message, with a better indication of the problem and a better guide to the solution.

Well, I hope you find this article useful.

Design Partitioning Based on Clock Domain

Introduction

When the system to design has several modules and each of these modules has its own clock, and the modules interact with each other, it is convenient to perform what is called partitioning based on clock domain, and follow a few simple rules regarding how to make the partition as well as how to name the I/O signals, and the communication signals between modules.

Partition Design

Suppose we have a system like the one shown in the figure below:

In this case the system has been divided into three modules A, B and C. This division is based on the different clocks in the system and the functionality of each module; so each module in this partition has its own clock. Thus, each module has what is commonly called its own clock domain (clock domain).
 

This partition of a system based on clock domain is important for several reasons, mainly it facilitates the work of the synthesis tool, improve the calculation task of the static timing analysis tool, save working time for the place and route tool. Another advantage of such partitioning is that it saves a lot of CPU processing time in complex systems.

Synchronizers

By making the partition based clock domain, and if the modules must interact with each other is needed some kind of synchronization between the communication signals, as each signal has its own clock domain. This synchronization can be performed by synchronizers or by FIFOs (not the purpose of this blog to explain the different methods of synchronization). For example, if a signal from Module A needs to be read in Module B a synchronizer is needed that synchronizes the signal from the A module based on the aclk clock, with the bclk clock of the module B. Similarly, if you want to send a signal from the Module B to the module A, a synchronizer is required to pass from the bclk domain to the aclk domain.
 

Thus, all main modules has only a single clock, while synchronizer modules have multiple clocks.

Signals Naming

With this type of partition is easier to follow a naming convention for the signals. Thus, all signals that are only controlled by a single clock, are named by referencing the clock domain names. For example the signals of the module A that are only controlled by the clock A, aclk, can be named beginning with the letter a (referencing the module A), so you can name the signals as adata, aaddr, aen, etc.. the same for signals controlled by blck, Module B, bdata, baddr, ben, etc.
 

On the other hand signals that cross clock domains (through synchronizers) should be named in such a way to facilitate the origin and destination of the signal. For example, if the signal ack must cross the bclk domain to the aclk domain, it could be named b2a_ack.
 

Using this type of naming convention can easily identify what are the different signals crossing clock domains. One of the great advantages of doing this is that you can write the corresponding constraint of false path to ease the work of static analysis tool time.

Other Benefits of Partition by Domain Clock

In addition to ease of timing closure, the advantages of design partitioning are better floorplanning for synthesis and; therefore, a reduction in area, performance, and potentially lower power. The synthesis tool is able to do a better job because there is only one clock in the module and the design can be easily optimized for area, speed, or power.
Also, by having the clock domain separated modules, existing synthesis tools allow each module to be individually optimized (either per area, speed or power). 

It's all for today .....

I hope to be useful .....

Reducing Compiling Time in Quartus II

Simple Tip to Save you Some Priceless Time !

In order to reduce compilation time use the rapid recompile option:

On Quartus settings dialog box (Assignments menu -> Settings) under Compilation Process Settings -> Incremental Compilation, turn the Rapid Recompile option ON.

With this option ON, the compiler reuse compilation results to update design for small changes. 

Another option to reduce compilation time is to configure Quartus to use all the processors available in the PC running Quartus. 

Compilation Process Settings -> Parallel Compilation -> Use All Available Processors

One last option is to use the Smart Compilation option. Smart compilation can reduce compilation time by skipping compiler stages that are not required to recompile the design. Smart compilation skips entire compiler stages (such as Analysis and Synthesis) when they are not required. This feature is different from incremental compilation, which you can use to compile parts of your design while preserving results for unchanged parts. 

Compilation Process Settings -> Smart Compilation, turn the Smart Compilation option  ON.

Note: these are simple solutions to simple designs. For complex designs there are other options that will be detailed in other blog.  

Quartus-ModelSim: How to customize the waveforms to facilitate the debug

In a previous blog I described how to customize the waveforms in ModelSim in the Xilinx ISE environment. Due to the request of many of you, I now describe the waveform customization for the Altera Quartus users.  

As you'll read in the application note that I present; when invoking any simulation (functional or gate level) from the Quartus environment, ModelSim is automatically started up, displaying the waveforms resulting from the test bench in the panel called Wave View. Due to the ModelSim's settings (detailed in a script file) by default, only the entity signals are displayed in the waveform viewer, no other signal ... So, once opened this Wave View window if you wish to display internal signals of the design under test, or change the position and / or color of the signals, or add dividers, and many other features offered by ModelSim, you can do it (following certain steps explained later), but once you close ModelSim all modifications are lost!. Hence, when you run the same simulation again, you must start again with the modifications. The problem sound familiar?????

In the 'Application Note' that I present here, I detail the steps to follow, so that when you invoke ModelSim from Quartus, the Wave View will contain all the information you set and saved for proper verification and easy debug.

Here is the link to download the 'Application Note':  AN-08 C7T

Until next time!