Error: "cannot match operand(s) in the condition to the corresponding edges. . ." "An edge descriptor must be applied to an expression of size 1"

Introduction

Recently a student of mine asked me to review her Verilog code because she had problems and could not find how the error was originated. Obviously, the synthesis tool used generated an error message, and obviously that message did not give any idea of ​​what was the source of the problem. The first thing I did, and that sometimes works for me, is to synthesize the code into the tool of competition (X or A), and .... the result was the same: encrypted error message. The second thing that I usually do in these cases is "google" the error message. I did that and I found nothing ! ... I had no other choice but to study the issue and try to find out the source of the error.
Below you can find details of the problem, error messages and finally the solution ....

Encrypted messages Error

ISE generates the following error message:


"ERROR:Xst:904 - "../../RTL_Src/semaforo.v" line 64: An edge descriptor must be applied to an expression of size 1."
 
The Quartus' error message:

"Error (10200): Verilog HDL Conditional Statement error at semaforo.v(64): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct"

The lines of code corresponding to the line number indicated by the error message are:

At first sight, there is nothing wrong with the code. I checked each statement of these lines, every symbol, every name many times and everything looked perfectly fine.
Another thing I did it was to go to the reference error message generated by the tool. When using ISE the error is Xst ISE: 904:

when you double-click on the link of the error, the following message shows up in ISE:

Does it helps the 'help' ?.... nooooo !!!

Quartus directly had no link or further explanation of the error message itself.

Well, after many workarounds; as always, the solution was very simple. Actually the problem was not in the code itself, but in the definition of clk and rst.

These are the first lines of code where E / S are defined:

Can you find the problem ? .....

PROHIBITED continuing reading before finding the error .... :)

Just for saving a few lines of code, clk and rst were defined in the same line as the two bits vectors sensor and button .... so clk and rst are actually defined as vectors of two bits, so the instruction negedge or posedge can not determine which edge to execute.

As usual,  once one found the error, one says: "How come I can’t find it sooner!", "How easy is the solution !", etc. etc ... What I did find strange is that compilers can not generate a simpler error message, with a better indication of the problem and a better guide to the solution.

Well, I hope you find this article useful.

Reducing Compiling Time in Quartus II

Simple Tip to Save you Some Priceless Time !

In order to reduce compilation time use the rapid recompile option:

On Quartus settings dialog box (Assignments menu -> Settings) under Compilation Process Settings -> Incremental Compilation, turn the Rapid Recompile option ON.

With this option ON, the compiler reuse compilation results to update design for small changes. 

Another option to reduce compilation time is to configure Quartus to use all the processors available in the PC running Quartus. 

Compilation Process Settings -> Parallel Compilation -> Use All Available Processors

One last option is to use the Smart Compilation option. Smart compilation can reduce compilation time by skipping compiler stages that are not required to recompile the design. Smart compilation skips entire compiler stages (such as Analysis and Synthesis) when they are not required. This feature is different from incremental compilation, which you can use to compile parts of your design while preserving results for unchanged parts. 

Compilation Process Settings -> Smart Compilation, turn the Smart Compilation option  ON.

Note: these are simple solutions to simple designs. For complex designs there are other options that will be detailed in other blog.  

Quartus-ModelSim: How to customize the waveforms to facilitate the debug

In a previous blog I described how to customize the waveforms in ModelSim in the Xilinx ISE environment. Due to the request of many of you, I now describe the waveform customization for the Altera Quartus users.  

As you'll read in the application note that I present; when invoking any simulation (functional or gate level) from the Quartus environment, ModelSim is automatically started up, displaying the waveforms resulting from the test bench in the panel called Wave View. Due to the ModelSim's settings (detailed in a script file) by default, only the entity signals are displayed in the waveform viewer, no other signal ... So, once opened this Wave View window if you wish to display internal signals of the design under test, or change the position and / or color of the signals, or add dividers, and many other features offered by ModelSim, you can do it (following certain steps explained later), but once you close ModelSim all modifications are lost!. Hence, when you run the same simulation again, you must start again with the modifications. The problem sound familiar?????

In the 'Application Note' that I present here, I detail the steps to follow, so that when you invoke ModelSim from Quartus, the Wave View will contain all the information you set and saved for proper verification and easy debug.

Here is the link to download the 'Application Note':  AN-08 C7T

Until next time!