HDL-FPGA Coding Style Guide

Based on all my years of professional and educational experience I'd like to introduce a document detailing general guidelines for VHDL coding style as well as some related to FPGA architecture. 

Even though I've tried to summarize the most important points, it results in a lengthy document, but it still is useful when starting a new project, or as a reference for coding in HDL (VHDL or Verilog) / FPGA.

Link to the document is as follows. ..... ;) ......

Suggestions are welcome in case any of you have a 'guide/point' that I've missed in the doc.

Have a GrAt DaY ! 

Filtering Warning/Info Messages in ISE

Introduction 

After executing some of the available processes in the ISE environment, various and numerous messages are generated. These messages let the designer know the “health” of the project. In some cases, you may want to suppress a particular message from appearing in the “Errors and Warnings Report”. For example, you may get a Warning message about unconnected pins that you intend to be unconnected. ISE allows you to suppress, actually filter, a particular message from subsequent runs of the software. The tool you can use for this purpose is the “Message Filters”.

Messages That Can Be Filtered

Not all the message generated by the different processes can be filtered. You can filter messages that begin with "WARNING" or "INFO" and are followed by a library name and message number. For example, the following message can be filtered:

In this Warning message, Xst is the library name, and 2677 is the warning message number.

Note: ERROR messages cannot be filtered. Likewise, messages for some processes cannot be filtered (for example, messages generated by third-party software, such as the Synopsys software). Anyway, if you try to filter a message that cannot be filtered, a dialog box will come up stating that the message cannot be filtered.

Procedures to Filter Messages in ISE

1. Once you have your project open, enable message filtering as follows:
• Open the Design Summary pane by doing Project -> Design Summary/Reports.
• In the upper pane of the Design Summary, in the Design Overview, select Summary.
• In the button pane of the Design Summary, select Enable Message Filtering.
• 

• Note: it is also possible to enable message filtering from the project properties options available at: Project -> Design Properties in the Project Settings pane.

1. In the Processes pane of Project Navigator, run the process which generate the messages to be filtered. For instance execute the Synthesize-XST process.
2. In the Design Summary pane, and in the option Errors and Warnings, select the process that generate the messages to be filtered, for instance select Synthesis Messages to filter the messages generated by the synthesis tool. Then, in the main Project Navigator window all the Warnings, Infos and Errors messages related to the synthesis tool should be displayed
3. To select which messages should be filtered, in the pane listing all the messages highlight (left mouse click) the message to be filtered. If there are several messages of the same type, just select one. Then right-click on the message to filter, and select:
• Filter All Instances of This Message - to filter out all messages with the same library name and message number, regardless of the message text.
• Note: there is another options in the filtering menu:
• Filter This Instance Only - to filter out all messages with the same library name, message number, and text. This option is for just one message in particular, for instance for a specific bit of a bus.
4. Just to be sure the filter has been correctly setting up, do Edit -> Message Filters, a new window will come up in which the selected Warning/Info to be filtered will be detailed. 
• 
5. In this window you can:
• Remove the filter: right-click the filter and select Remove, or click the Remove filter(s) button.
• Temporarily disable a filter, right-click the filter and select Disable.
• Activate a disabled filter, right click the Enable.
6. Re-run the process generating the messages to be filtered. Then, from both the console as well as from the Error and Warning pane the messages should be filtered.

• 
  
7. Note: Still the filtered messages are available. Select All Implementation Messages under the Errors and Warnings option in the Design Summary pane. The filtered messages will be displayed with a Yes in the Filtered column.

Caution! 

When you suppress a message, it does not fix the issue. 

Do not filter messages for issues that must be fixed. 

Filter when you know what you are doing. Then, you can focus in warnings that you do need to fix.

Design Partitioning Based on Clock Domain

Introduction

When the system to design has several modules and each of these modules has its own clock, and the modules interact with each other, it is convenient to perform what is called partitioning based on clock domain, and follow a few simple rules regarding how to make the partition as well as how to name the I/O signals, and the communication signals between modules.

Partition Design

Suppose we have a system like the one shown in the figure below:

In this case the system has been divided into three modules A, B and C. This division is based on the different clocks in the system and the functionality of each module; so each module in this partition has its own clock. Thus, each module has what is commonly called its own clock domain (clock domain).
 

This partition of a system based on clock domain is important for several reasons, mainly it facilitates the work of the synthesis tool, improve the calculation task of the static timing analysis tool, save working time for the place and route tool. Another advantage of such partitioning is that it saves a lot of CPU processing time in complex systems.

Synchronizers

By making the partition based clock domain, and if the modules must interact with each other is needed some kind of synchronization between the communication signals, as each signal has its own clock domain. This synchronization can be performed by synchronizers or by FIFOs (not the purpose of this blog to explain the different methods of synchronization). For example, if a signal from Module A needs to be read in Module B a synchronizer is needed that synchronizes the signal from the A module based on the aclk clock, with the bclk clock of the module B. Similarly, if you want to send a signal from the Module B to the module A, a synchronizer is required to pass from the bclk domain to the aclk domain.
 

Thus, all main modules has only a single clock, while synchronizer modules have multiple clocks.

Signals Naming

With this type of partition is easier to follow a naming convention for the signals. Thus, all signals that are only controlled by a single clock, are named by referencing the clock domain names. For example the signals of the module A that are only controlled by the clock A, aclk, can be named beginning with the letter a (referencing the module A), so you can name the signals as adata, aaddr, aen, etc.. the same for signals controlled by blck, Module B, bdata, baddr, ben, etc.
 

On the other hand signals that cross clock domains (through synchronizers) should be named in such a way to facilitate the origin and destination of the signal. For example, if the signal ack must cross the bclk domain to the aclk domain, it could be named b2a_ack.
 

Using this type of naming convention can easily identify what are the different signals crossing clock domains. One of the great advantages of doing this is that you can write the corresponding constraint of false path to ease the work of static analysis tool time.

Other Benefits of Partition by Domain Clock

In addition to ease of timing closure, the advantages of design partitioning are better floorplanning for synthesis and; therefore, a reduction in area, performance, and potentially lower power. The synthesis tool is able to do a better job because there is only one clock in the module and the design can be easily optimized for area, speed, or power.
Also, by having the clock domain separated modules, existing synthesis tools allow each module to be individually optimized (either per area, speed or power). 

It's all for today .....

I hope to be useful .....

"Warning: NUMERIC_STD, "=": metavalue detected, returning FALSE". ISim, Xilinx

Introduction 

Whenever it’s possible I avoid using ISIM (the ISE embedded simulator). Among other things, it has poor support, and also very encrypted Warnings and Errors messages. In the last project I worked, I had no choice but using ISim, and when I was finishing the top level simulation I got the famous warning "Warning: NUMERIC_STD," = "metavalue detected, returning FALSE". And I say famous, because I goggled it in the web and found many entries, but almost none gave me an idea of what happened and even less how to fix it. Well, that is the reason I’m writing this post, to tell you what this means and at least one concrete way to find a clue where or how this Warning is generated.

What is it "Metavalue Detected" ? 

This message means that the simulator encountered as a result of an expression a non-numeric value, which can be for example "UUUU" or "XXXX" or some other value.

Commonly this result is obtained during the initialization of the system under test, and depending on the type of test it can repeat this message periodically or just once. As an example,  in the following figure you can read the messages I got during my simulation.

How to find the source of the warning message? 

As it can be seen from the figure shown above, there is nothing that looks "rare/strange" in the waveform of the various signals shown, so that, the solution is not at simple sight.

One way to find the source of this warning message, at least in this particular case that I’m showing you, it is to try to see the different internal signals of the whole system described in VHDL. To do this, go to the panel called "Instance and Processes" and click on the arrow that is next to the test bench, show in the figure above, click on the arrow next to top_tb. The name of the instance of the component under test in the test bench appears, in this case I called 'uut'. Again click on the arrow that is next to 'uut' and the various sub-components of the system are now listed. The following figure details what it was explained.

The next step is to select each sub-component and adding the different E/S and internal signals to the waveforms window (Wave Window). Select a sub-component by simply click on its name, then in the 'Objects' panel all the E / S and internal signals  of this sub-component appear. Then select all signals (because we do not know which one is malfunctioning), and add then to the Wave Window.

The following figure details the steps explained.

In the figure above, I have added to the Wave Window all the signals of the cont_4bits_1 sub-component. I can also add the signals of the other sub-components, freq_div_1 and bcd_7seg_1, but it happened that just adding the signals of cont_4bits_1, I found part of the problem. How? ... Well, once I added the signals of this sub-component, I run the simulation again, and immediately I visualized something that caught my attention .... what was that? .. well, try to find it out by yourself in the following figure.:

What do you see weird ???? .......

Yes ! ( I guess you found it out J )…  the last two signals, count and i_count, are not defined ('U' = undefined) .... We found something! ....

Possible Solutions

Now I come to this point, the steps to follow are two:

1) review the VHDL / Verilog subcomponent cont_4bits_1, and check especially initializing the count and i_count vectors.

2) review the bench test and verify the value given to the signal that initializes the system, commonly called reset.

In one of the two sides is the origin of Warning, and the solution to work with .....! ... (In my particular case it was a no well defined reset value in the test bench....).

Finally a note for those using ModelSim, you can read in various forums that ModelSim has an option for this type of Warnings (based on 'metavalues') that allow you to ignore them. Of course I DO NOT share that view, because it is always good to know the origin of the Warning. In my particular case if I had used ModelSim and had used the option to ignore these Warning, I had never encountered the problem that I found with the reset signal. . .

Well, I hope you find it useful ... reminded me if so!

See you soon ...

Reducing Compiling Time in Quartus II

Simple Tip to Save you Some Priceless Time !

In order to reduce compilation time use the rapid recompile option:

On Quartus settings dialog box (Assignments menu -> Settings) under Compilation Process Settings -> Incremental Compilation, turn the Rapid Recompile option ON.

With this option ON, the compiler reuse compilation results to update design for small changes. 

Another option to reduce compilation time is to configure Quartus to use all the processors available in the PC running Quartus. 

Compilation Process Settings -> Parallel Compilation -> Use All Available Processors

One last option is to use the Smart Compilation option. Smart compilation can reduce compilation time by skipping compiler stages that are not required to recompile the design. Smart compilation skips entire compiler stages (such as Analysis and Synthesis) when they are not required. This feature is different from incremental compilation, which you can use to compile parts of your design while preserving results for unchanged parts. 

Compilation Process Settings -> Smart Compilation, turn the Smart Compilation option  ON.

Note: these are simple solutions to simple designs. For complex designs there are other options that will be detailed in other blog.  

Quartus-ModelSim: How to customize the waveforms to facilitate the debug

In a previous blog I described how to customize the waveforms in ModelSim in the Xilinx ISE environment. Due to the request of many of you, I now describe the waveform customization for the Altera Quartus users.  

As you'll read in the application note that I present; when invoking any simulation (functional or gate level) from the Quartus environment, ModelSim is automatically started up, displaying the waveforms resulting from the test bench in the panel called Wave View. Due to the ModelSim's settings (detailed in a script file) by default, only the entity signals are displayed in the waveform viewer, no other signal ... So, once opened this Wave View window if you wish to display internal signals of the design under test, or change the position and / or color of the signals, or add dividers, and many other features offered by ModelSim, you can do it (following certain steps explained later), but once you close ModelSim all modifications are lost!. Hence, when you run the same simulation again, you must start again with the modifications. The problem sound familiar?????

In the 'Application Note' that I present here, I detail the steps to follow, so that when you invoke ModelSim from Quartus, the Wave View will contain all the information you set and saved for proper verification and easy debug.

Here is the link to download the 'Application Note':  AN-08 C7T

Until next time!

ASCII to HEX - the smart way....

Introduction

In this post I'll present an easy way to convert text in ASCII to Hex. This is useful to save data in memory, pass through data in a particular communication protocol, a data to be displayed on an LCD, etc..

Procedure

The VHDL standard has defined several type of conversion's functions in its standard libraries. Some of this functions will be used for this conversion.

The necessary steps for conversion are as follows:

1 - Declaration of the string, constant and signal counter in the declarative part of the architecture:

 1 architecture beh of test is
 2 .......
 3 constant N : natural := 16;
 4 type tstring is array(natural range<>) of character;
 5 constant msje1 : tstring(0 to N-1) := "Vuelvo en 5 ... ";
 6 .......
 7 -- declaracion de la senal para asignar el Hex correspondiente
 8 signal byte_to_Tx: std_logic_vector(7 downto 0);
 9
10 -- declaracion de contador
11 signal char_cont: natural range 0 to N-1;
12 .......

2 - Using conversion functions to get the Hexadeciaml byte for each character in the string:

byte_to_tx<=std_logic_vector(to_unsigned(character'pos(msje1(char_cont)),8));

Let's consider this last statement piece by piece:
a-

msje1(char_cont);

what makes this part of the instruction is to position in a specific character of the msje1. The position is given by the counter's value char_cont. Of course, this statement must be inside a loop where the counter is incremented once is sent the respective character.

b-

character'pos('character')

in this part 'character' represents the character of msje1 specified by char_cnt. On the other hand, character'pos ('V') (I write 'V' as an example of a character from msje1), what it does is first to return the position number value for the  'V' character in the array defined in the VHDL standard. To refresh a little bit something that your surely saw some time ago, I detail the type character as it's defined in the VHDL standard: 

 1 type character is (
 2     NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
 3     BS, HT, LF, VT, FF, CR, SO, SI,
 4     DEL, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
 5     CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
 6     ‘ ’,’!’, “”,’#’,’$’,’%’,’&’,’’’,
 7     ‘(‘,’)’,’*’, ‘+’, ‘,’,’-‘,’.’,’/’,
 8     ‘0’,’1’,’2’,’3’,’4’,’5’,’6’,’7’,
 9     ’8’,’9’,’:’,’;’,’<’,’=’,’>’,’?’,
10     ‘@’,’A’,’B’,’C’,’D’,’E’,’F’,’G’,
11     ‘H’,’’I’,’J’,’K’,’L’,’M’,’N’,’O’,
12     ‘P’,’Q’,’R’,’S’,’T’,’U’,’V’,’W’,
13     ‘X’,’Y’,’Z’,’[‘,’\’,’]’,’^’,’_’,
14     ‘`’,’a’,’b’,’c’,’d’,’e’,’f’,’g’,
15     ‘h’,’i’,’j’,’k’,’l’,’m’,’n’,’o’,
16     ‘p’,’q’,’r’,’s’,’t’,’u’,’v’,’w’,
17     ‘x’,’y’,’z’,’{‘,’|’,’}’,’~’,DEL);
18

as you can see, the character 'V' is positioned in 86th place in the array, so the character'pos ('V') returns the number 86 (as an integer).

c-
So now we have to convert an integer, 86, (which is giving me the position) to std_logic_vector. Using the now 'famous' conversion functions table  we know that we must first pass the integer to unsigned and then to std_logic_vector. That is done by the next part of the statement:

std_logic_vector(to_unsigned(86,8));

where 8 is the number of bits needed to represent the maximum number estimated to be converted (in this case 256).

d-
finally the binary corresponding to the character specified by char_cont signal is assigned to byte_to_Tx

Final ...

I hope you find it useful ... and if you ever use NOTIFY ....

See you soon ....

Combinational Loop

Introduction

Combinational loops are logical structures that contain no synchronous feedback element. This kind of loops cause stability and reliability problemas,  as we will see in this article, violating the synchronous principles by making feedback with no register in the loop.

Why? How? is generated a combinational loop? 

Basically, a combinational loop es implemented in hardware (gates) when in the written VHDL code describing combinational logic a signal that is in the left side of an assignment statement (that is, to the left of the <= symbol) it also is on the expression at the right side of the signal assignment statement (right of <=). For example the following lines of code generate a combinational loop, as long as they are written in a combinational process or in a concurrent signal assignment statement.

1 acc <= acc + data;
2
3 Z <= Z nand B;
4
5 cnt <= cnt + 1;

However, it's important to point out that if these same statements are written in a clocked process, each of them will generate the respective sequential logic. This is due to the fact that the signal assignment statement in clocked process will generate a register for the assigned signal, therefore the loop will be registered in this case, therefore no combinational loop is generated.

Hardware

The following figure shows a diagram of a combinational loop. 

As it is shown in the figure, the combinational logic output is fedbacked to the same combinational logic without any register in the loop. The logic between the first input an the last output can be made up of one or several levels of combinational logic. It can also have different signals coming in and coming out of that piece of logic, but at least one of the signal is going back (feedback) to the first logic level, as it can be seen in the following figure.

This kind of logic circuit usually is not desired, no wanted to be implemented. Hence, when the synthesis tool finds out about this combinational loop generates a warning message. 

Here is an example of VHDL code that generate a combinational loop when is implemented.

 1 library ieee;
 2 use ieee.std_logic_1164.all;
 3
 4 entity lazo_comb is
 5   port(
 6     a: in  std_logic;
 7     z: out std_logic);
 8 end lazo_comb;
 9
10 architecture beh of lazo_comb is
11
12  signal y: std_logic;
 
13
14 begin
15     z <= y;
16
17 process(a,y)
18  begin
19     y <= y nand a;
20 end process;
21
22 end beh;

The synthesis tool, Synplify in this case, generates the following warning regarding the combinational loop. 

The warning message "found combinational loop at 'y'" means that the signal 'y' is feed-backed to the input of the combinational logic without any register in the loop. This loop can be easily found when seeing the RTL view of the synthesized system, as it can be seen in the following figure. 

Simulation

The simulation of the system (very simple system) is shown in the following figure. 

The ModelSim windows details a lot of information that deserve a detailed analysis. First of all, the top window plots the waveforms of the signals from the described system, whose main expression is in the line 24 of the middle window. The bottom window, Transcript window, generates an error message, saying that the limit of iterations has been reached at 50ns and no stable value has been gotten. In other words, this mean that the system has began to oscillated and remained oscillating. The maximum number of iterations is configurable in ModelSim (Simulate->Runtime Options); as it's in most simulators. By default this value is set to 5000. Another important piece of information can be found in the bottom of the waveform window. There you can read that the number of Delta reached 5000, which is exactly the number maximum of iterations set in the runtime options, and even after that amount of deltas the system is not stable.
Why this simple logic is oscillating? Well, analyzing the true table of the nand gate, while one of the input is stuck at '0', the output will be always '1'. That is happening in the simulation shown above. Whereas, when the input (signal a in the simulation) tries to change to '1', due to the fact the other input is still at '1' the output change to '0', then since the feedback input is '0', the output should go to '1', then that '1' is going back with the other input at '1', the output will go to '0' again, and so on...This is what is called an "unstable combinational loop". This kind of loop should NEVER be used in a real design.

Other point to bring out on this example is the importance of simulating a system. Assuming that we configured the FPGA without any simulation, based on the fact that the synthesis tool just gave us a 'warning'), we'd see an no stable output, spending some time (maybe a lot of time) trying to find out why the output is not stable. Conversely, by doing the simulation the problem would appear at first shot. 

 Code Style

In designs with a large, very large, amount of code lines it is very easy to make mistakes and generate a combinational loop with no intention (as it can be seen in the example above). So, follow certain order when writting the code, trying to maintain a certain flow of data. Also, take a close look at the warnings generated by the synthesis tool. 

In case you deliberately want to implement a combinational loop, write a detailed description of the reason for doing that, and also write a comment in the constraint file. The reason for this last point is due to the fact that the Static Timing Analysis tool (STA) usually increase the minimum period of the system when it founds a combinational loop. Therefore, in this case you should tell to the STA tool to 'ignore' that particular path. The syntax for ignoring a path is 'set_false_path' for the Quartus (Altera) software, and for the ISE (Xilinx) you should use TIG with its resepctivs syntax in both cases.