Introduction
For some people learning the language the concept of delta time is one of the most tough to understand. It's not the objective of this article to discuss about delta delay, but to let you to know the tools available in ModelSim to 'see' the delta delays.
How to 'see' the delta delays
I'll explain in few steps the procedures to follow to find out how many delta delays happens until a signal has an stable value.First, here is the simple code I'll use
1 library ieee;
2 use eee.std_logic_1164.all;
3
4 entity aoi is
5 port(A, B, C, D: in std_logic;
6 E : out std_logic);
7 end aoi;
8
9 architecture beha4 of aoi is
10 signal O1, O2, O3:std_logic;
11
12 begin
13 b4: process(A, B, C, D, O1, O2, O3)
14 begin
15 E <= not O3;
16 O1 <= A and B;
17 O2 <= C and D;
18 O3 <= O1 or O2;
19 end process b4;
20 end dflow1;
2 use eee.std_logic_1164.all;
3
4 entity aoi is
5 port(A, B, C, D: in std_logic;
6 E : out std_logic);
7 end aoi;
8
9 architecture beha4 of aoi is
10 signal O1, O2, O3:std_logic;
11
12 begin
13 b4: process(A, B, C, D, O1, O2, O3)
14 begin
15 E <= not O3;
16 O1 <= A and B;
17 O2 <= C and D;
18 O3 <= O1 or O2;
19 end process b4;
20 end dflow1;
and this is the simple test bench used
1 library ieee;
2 use eee.std_logic_1164.all;
3
4 entity aoi_tb is
5 end aoi_tb;
6
7 architecture test of aoi_tb is
8 signal O1, O2, O3 : std_logic;
9 signal a, b, c, d, e: std_logic;
10 component aoi is
11 port(A, B, C, D: in std_logic; E: out std_logic);
12 end component;
13
14 begin
15 a <= '0', '1' after 6 ns;
16 b <= '0', '1' after 5 ns, '0' after 8 ns;
17 c <= '0', '1' after 7 ns;
18 d <= '0';
19
20 uut: aoi port map(
21 E => e, a => a ,b => b ,c => c, d => d
22 );
23 end test;
24
2 use eee.std_logic_1164.all;
3
4 entity aoi_tb is
5 end aoi_tb;
6
7 architecture test of aoi_tb is
8 signal O1, O2, O3 : std_logic;
9 signal a, b, c, d, e: std_logic;
10 component aoi is
11 port(A, B, C, D: in std_logic; E: out std_logic);
12 end component;
13
14 begin
15 a <= '0', '1' after 6 ns;
16 b <= '0', '1' after 5 ns, '0' after 8 ns;
17 c <= '0', '1' after 7 ns;
18 d <= '0';
19
20 uut: aoi port map(
21 E => e, a => a ,b => b ,c => c, d => d
22 );
23 end test;
24
Once you have executed the test bench, the Wave window will show the respective waveform, as you can see in this figure (a point to keep in mind is that you will likely have to add the internal signals, in this case O1, O2, O3, to the Wave window):
So, if you want to know the delta delays that happened at the simulation time 8 ns, you have to:
1- Place a cursor on the 8 ns simulation time.
2- Click on the 'Expanded Time Delta Mode" button
3- Click on the "Expand Time at Active Cursor" button
4- Click on the "Zoom In At Active Cursor"
5- ReAdY !
The following figure details the above steps and the expected result.
Other way
ModelSim offers another way of seeing the delta delay. In the 'View->List' option, the signals and their respective events and delay are detailed in a table.
The following figure is the respective 'list' of the above case.
FINALLY
So, if you ever had doubt on how the delta delays works, here is an easy way of find it out !.See you soon....
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