Design Partitioning Based on Clock Domain

Introduction

When the system to design has several modules and each of these modules has its own clock, and the modules interact with each other, it is convenient to perform what is called partitioning based on clock domain, and follow a few simple rules regarding how to make the partition as well as how to name the I/O signals, and the communication signals between modules.

Partition Design

Suppose we have a system like the one shown in the figure below:

In this case the system has been divided into three modules A, B and C. This division is based on the different clocks in the system and the functionality of each module; so each module in this partition has its own clock. Thus, each module has what is commonly called its own clock domain (clock domain).
 

This partition of a system based on clock domain is important for several reasons, mainly it facilitates the work of the synthesis tool, improve the calculation task of the static timing analysis tool, save working time for the place and route tool. Another advantage of such partitioning is that it saves a lot of CPU processing time in complex systems.

Synchronizers

By making the partition based clock domain, and if the modules must interact with each other is needed some kind of synchronization between the communication signals, as each signal has its own clock domain. This synchronization can be performed by synchronizers or by FIFOs (not the purpose of this blog to explain the different methods of synchronization). For example, if a signal from Module A needs to be read in Module B a synchronizer is needed that synchronizes the signal from the A module based on the aclk clock, with the bclk clock of the module B. Similarly, if you want to send a signal from the Module B to the module A, a synchronizer is required to pass from the bclk domain to the aclk domain.
 

Thus, all main modules has only a single clock, while synchronizer modules have multiple clocks.

Signals Naming

With this type of partition is easier to follow a naming convention for the signals. Thus, all signals that are only controlled by a single clock, are named by referencing the clock domain names. For example the signals of the module A that are only controlled by the clock A, aclk, can be named beginning with the letter a (referencing the module A), so you can name the signals as adata, aaddr, aen, etc.. the same for signals controlled by blck, Module B, bdata, baddr, ben, etc.
 

On the other hand signals that cross clock domains (through synchronizers) should be named in such a way to facilitate the origin and destination of the signal. For example, if the signal ack must cross the bclk domain to the aclk domain, it could be named b2a_ack.
 

Using this type of naming convention can easily identify what are the different signals crossing clock domains. One of the great advantages of doing this is that you can write the corresponding constraint of false path to ease the work of static analysis tool time.

Other Benefits of Partition by Domain Clock

In addition to ease of timing closure, the advantages of design partitioning are better floorplanning for synthesis and; therefore, a reduction in area, performance, and potentially lower power. The synthesis tool is able to do a better job because there is only one clock in the module and the design can be easily optimized for area, speed, or power.
Also, by having the clock domain separated modules, existing synthesis tools allow each module to be individually optimized (either per area, speed or power). 

It's all for today .....

I hope to be useful .....